1. Field of the Invention
This invention relates to the fabrication of high resolution shadow masks for electron, ion beam and X-ray lithography, ion implantation, and ion etching.
2. Background Art
Charged particle beams (electron or ion) are widely used in the fabrication of semiconductor devices. In order to achieve the high resolution required for lithographic applications, the beams are focused down to a small spot which is then scanned across the substrate. Due to the small spot sizes, the scanning time can be quite long when large areas need to be covered. One alternative to focused beam scanning is to use broad area beams with the pattern definition provided by shadow masks. A shadow mask consists of a thin substrate (typically a membrane) which has been patterned with holes that allow passage of the ions or electrons through the mask. This approach allows for the simultaneous processing of many pattern elements over a wide area and consequently greatly improves the speed of the lithographic process.
Shadow masks may be used either in a proximity mode or in a projection type system. In a proximity process the mask is placed in very close proximity to the wafer to be patterned. The pattern transfer to the wafer occurs by simple shadowing and the mask pattern is reproduced on the wafer at a 1-to-1 size ratio. In a projection system, the mask is positioned in a lens system such that the pattern of ions or electrons leaving the mask can be focused onto the wafer even though the mask and wafer are not physically in close contact. A projection system may be 1-to-1 or it may operate with a magnification factor.
Shadow masks are also potentially useful for ion implantation or etching. In these processes as generally practiced, masking layers are applied to a surface of each wafer individually. The masking layers are then patterned using standard lithographic techniques. Each wafer is exposed to the ion beam with the pattern definition provided by the masking layer. After completing the implantation or etching process, the mask layers must then be removed. The use of shadow masks to provide the pattern definition would eliminate the need to apply and pattern masking layers on each wafer and would thereby significantly reduce the amount of processing required.
The use of silicon shadow masks for ion implantation has been disclosed by Lepselter et al. in U.S. Pat. No. 3,713,922. The masks described by Lepselter consist of thin membranes of silicon supported by a grid of thicker reinforcing ribs. The membranes are of n-type material and are formed by a preferential etch-stop technique using n+ doped support wafers. The use of a reinforcing grid is a severe limitation since it restricts the die sizes that can be patterned. Lepselter suggests die sizes from 50 to 500 microns using this technique. Currently, very large scale integrated (VLSI) circuit designs call for die sizes having lateral dimensions of up to 12 to 15 mm. Future developments in VLSI technology are anticipated to require even larger die sizes. In order to be practically useful for such large die sizes, shadow masks should have self-supporting membranes of at least several centimeters in lateral dimension.
Alternative shadow mask techniques are disclosed by Magdo et al. in U.S. Pat. No. 4,256,532; by Bohlen et al. in U.S. Pat. Nos. 4,417,946 and 4,448,865; and by Behringer in U.S. Pat. No. 4,589,952. The basic membrane fabrication technique used in all of these inventions is to produce a highly doped p+ membrane by preferentially etching a lightly doped substrate.
The methods of Lepselter, Bohlen, and Behringer all define the circuit pattern on the shadow mask prior to forming the membrane. To do this, the silicon layer that will ultimately form the membrane is first patterned while the support wafer is still intact. The support wafter is subsequently etched away in the region that will be the membrane. Magdo uses the reverse sequence in that the membrane is formed first by etching away the underlying substrate and then the membrane is patterned to produce the shadow mask.
In order to produce a shadow mask that is useful for semiconductor manufacturing, several requirements must be met. Typical pattern elements in VLSI designs are now below 1 micron in size and future developments anticipate features as small as 0.25 microns. Therefore, any shadow masking technique must be capable of producing masks with openings in this size range. As discussed above, die sizes require that the self-supporting mask area must be at least several centimeters in size. An additional requirement that is particularly important for shadow masks is that pattern distortion must be kept below certain limits. Since typical integrated circuit designs have multiple patterning layers, in order for the final device to function properly the pattern of each layer must be in precise registration with all other layers. Typical requirements are that pattern distortion must be maintained at one tenth of the minimum feature size over the area of the die. For the die sizes and feature sizes discussed above, this requirement translates into the restriction that pattern placement of features on the mask must be accurate to within a few parts per million over the mask area, or to within tolerances as small as 100 nm.
The requirement of low pattern distortion places an important restriction on the value of internal stress allowed in the membrane. This subject is considered in detail by Randall et al., "The Thermomechanical Stability of Ion Beam Masking", Journal of Vacuum Science Technology, B5(1), Jan./Feb. 1987, pp. 223-227. The general conclusion of this work is that to achieve acceptable distortion levels the tensile stress of the silicon membrane must be controlled to be lower than 3.times.10.sup.8 dynes/cm.sup.2. This same consideration carries over to any additional layers that are applied to the silicon membrane.
A countervailing consideration is that the membrane must have enough tensile stress so that it remains flat. Flatness is required to insure that high resolution images can be formed on a circuit die using the membrane as a mask. The prior art for the fabrication of large area silicon shadow masks discussed above fails to deal with this problem adequately. Unless additional stress compensation techniques are applied, membranes made of p+ material on lightly doped substates will have stress levels several times higher than the range shown by Randall to be required. The stresses of the various masking layers employed is also not controlled in these processes. Therefore, one of the objects of this invention is to provide a process for the fabrication of silicon shadow masks which can maintain stress levels within the relatively limited range required so that low distortion masks can be produced.